Dynamic RAMs have been a major driving force behind VLSI technology development and their density and performance in terms of speed have increased at a very fast pace.
A most critical aspect of DRAM design is choosing a sensing scheme which can detect a small amount of charge transferred from a storage capacitor (cell) and then restore the charge back again. A typical DRAM sensing scheme involves pre-charging a bit line to a certain voltage, transferring a charge from a storage capacitor to the bit line to develop a signal on the bit line, sensing and amplifying this signal, and then restoring the charge to the storage capacitor.
As is well known in the art, the signal developed on the bit lines is highly dependent among other things, on the pre-charge voltage of the bit lines, and the bit line capacitances.
CMOS DRAMs, first introduced commercially in the 256K DRAM configuration were proven highly successful. By 1998 64 Megabit drams were available and 1 gigabit are now contemplated. These structures are the result of highly packed architectures in which the dimensions of the different elements become of the order of 0.20 .mu.m or less. Such tight packing necessitates lowering the power supply voltage from the original 5 volts to 3.5 volts for the 16 megabit DRAMs, to 2.5 volts for the 256 Megabit DRAMs and may reach low level of 1.5 volts for a 1 Gigabit structure.
In the past, typical pre-charge levels were 1/2 Vblh (high voltage applied to the bit line) as this tends to be a natural voltage for the bit-lines that is easy to obtain by an equalization circuit on the bit lines. However, as the power supply voltage is reduced and the bit-line high voltage becomes lower and lower, this also results in lowering the pre-charge level of the bit-lines to the point where the overdrive on the transfer gate during signal development becomes quite small, resulting in a long signal development time. Various pre-charging techniques for sensing circuits have been developed in an effort to compensate for this problem, among the most successful being techniques that pre-charge the bit lines to 2/3 of Vblh or more in cases of PMOS arrays, and to 1/3 or less in cases of NMOS arrays.
U.S. Pat. No. 5,416,371 shows one method that obtains the 2/3 Vblh pre-charge voltage by limiting the downward swing of the bit-lines to 1/3 Vblh. This solution requires a sophisticated and complex special driver circuit increasing the cost of production. The major problem in attempting to pre-charge the bit-lines to other than 1/2 Vblh is that what may be called as the natural or steady state of the circuit is with the bit lines at 1/2 Vblh due to the circuit symmetry that results in a charge distribution that tends to equalize the bit lines at 1/2 Vblh. Therefore any other equalization scheme requires a substantial power supply and time to pre-charge and maintain a voltage other than the 1/2 Vblh on the bit lines.
There remains, therefore a need for a scheme that will permit rapidly pre-charging the bit-lines to voltages other than the 1/2 Vblh without needing a substantial power supply in the equalization circuit.